University Park, Pa. -- A transistor model jointly developed by Penn State and Philips was designated an industrywide model for future chip design by the Compact Model Council (CMC). The winning design garnered a $40,000 prize from the council, which is the world's foremost authority for the standardization, implementation and use of transistor models. The group was formed in 1996 and comprises 31 leading semiconductor companies and circuit simulator suppliers.
In addition to the $40,000, the council will contribute an additional $120,000 in 2006 to the ongoing Penn State-Philips effort. The Penn State-Philips (PSP) complementary metal-oxide semiconductor (CMOS) transistor model will be the industry standard for simulating the behavior of new CMOS transistors produced at the 65-nanometer technology node and beyond. Engineers will be able to use the PSP model to accurately predict circuit performance before committing their designs to silicon.
"The PSP model incorporates a number of recent advances in metal-oxide semiconductor device physics and was made possible by the innovative but practical solution of several long-standing theoretical problems in compact metal-oxide semiconductor field-effect transistor modeling. This made it possible to include all relevant physical effects without significantly increasing model complexity -- a prerequisite for scalability of the model to ever-smaller device geometries," said Gennady Gildenblat, professor of electrical engineering and leader of PSP development at Penn State.
"As CMOS takes on new roles beyond the production of purely digital chips, it is important that the industry has a single model that accurately predicts transistor performance under all circuit conditions, including RF and analog circuit behavior," said Reinout Woltjer, head of Philips Research's Device Modeling Group. "By basing the PSP model on the fundamental physics of transistor operation, it provides extremely accurate results over the entire operating spectrum from DC to well in excess of 50 gigahertz."
Because it is based on the underlying physics of CMOS transistor operation, the PSP model needs significantly fewer parameters than those required by other models. This allows the PSP model to conduct circuit simulations faster and with more accurate results. The PSP model accurately models gate leakage, noise and quantum mechanical effects, all of which will become increasingly important to circuit performance as CMOS processes are scaled down to nanometer proportions.